Effective placement of chips on a shuttle mask

Shih-Ying Chen; Eric C. Lynn

doi:10.1117/12.504220

28 August 2003 Effective placement of chips on a shuttle mask

Shih-Ying Chen, Eric C. Lynn

Proceedings Volume 5130, Photomask and Next-Generation Lithography Mask Technology X; (2003) https://doi.org/10.1117/12.504220
Event: Photomask and Next Generation Lithography Mask Technology X, 2003, Yokohama, Japan

Abstract

An effective algorithm was developed to prepare a mask layout from several chip databases. The underlying idea is solving so called “strip packing” problems, which actually have been very common in many industries. A major difference between applications is the definition of cost function used in a particular packing problem. In the present case, the work is to test whether all component chips can fit onto a mask with limited area and how these chips are placed. Based upon this goal, the cost function is simply the minimum rectangle that can accommodate all chips. If the minimum enclosing rectangle is smaller than the available mask area, it is feasible to make up the desired mask. The algorithm also tells us the placement of all chips if the placement is possible. The computing time is very short, in the range of seconds, and expected to be short for most cases, too. After all, the changes in other cases are the number and sizes of rectangles. For an operation on GDSII files, the required process time is virtually the time of reading component databases and writing out the result database. This is a generic algorithm, so it does not reply on any particular tools. As long as a tool can perform common arithmetic operations and layout generation, it could be used to implement the job. This work eliminates the manual try-and-error packing process during the data preparation stage of a shuttle mask. Breaking one more bottleneck, which is the manual packing process, could significantly reduce the cycle time of mask data preparation.

Citation Download Citation

Shih-Ying Chen and Eric C. Lynn "Effective placement of chips on a shuttle mask", Proc. SPIE 5130, Photomask and Next-Generation Lithography Mask Technology X, (28 August 2003); https://doi.org/10.1117/12.504220

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