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12 December 2003 Design of a reconfigurable optical microprocessor for smart-pixel applications
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The ever increasing demand for communication bandwidth and system interconnectivity has been a motivating factor behind the integration of optoelectronics device and conventional data processing circuitry. Over the last two decades, fiber optic components have become the dominant technology in the telecommunications industry. In last 5 years, optical interconnection techniques have been suggested as a solution to the interconnect density and bandwidth problems faced by electrical systems at the cabinet, PC-board and even chip level. Based on the smart pixel architectures in the last decade, the proposed chip monolithically integrates optical sensors with silicon CMOS based circuitry. This project incorporates an instruction fetch unit (IFU), that fetches the instructions from an external host computer, and a 2D-array of one-bit smart pixels called the processing element (PE). Each PE consists of an ALU, control logic, dual port register memory bank, photo-receiver circuit and associated driver circuits. By tiling these smart pixels in 2D, it is possible to form a programmable smart pixel array that is well suited to read optical page-oriented data types. The CASPR chip contains a 4x4 array of PEs connected to a single IFU. Inter PE communication has been established through nearest neighbor communication. Simultaneous communication to all the PEs is possible through global communication. The instruction set for this architecture is 17-bit long. The chip has been successfully fabricated in 0.5μ technology. We present in this paper the design and initial test results from the recent fabrication.
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V. Sathya Vagheeswar, Shankar Raman Krishna Kumar, Arvind Chokhani, and Fred R. Beyette Jr. "Design of a reconfigurable optical microprocessor for smart-pixel applications", Proc. SPIE 5201, Photonic Devices and Algorithms for Computing V, (12 December 2003);

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