19 November 2003 An efficient JPEG2000 encoder implemented on a platform FPGA
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While the recent JPEG2000 standard only specifies the bitstream and file formats to ensure interoperability, it leaves the actual implementation up to the designer. Like many DSP applications, there are a number of implementation platform options for the designer. This paper gives a complexity analysis of an implementation of a JPEG2000 encoder using a hardware/software co-design methodology on a Xilinx Virtex-II(TM) platform FPGA. Central to the performance of the encoder is a high-throughput tier-1 entropy coder. This paper will describe the encoder design targeted for video surveillance applications, and will compare and contrast with two other implementation options.
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Paul R. Schumacher, Mark Paluszkiewicz, Rick Ballantyne, Robert Turney, "An efficient JPEG2000 encoder implemented on a platform FPGA", Proc. SPIE 5203, Applications of Digital Image Processing XXVI, (19 November 2003); doi: 10.1117/12.512542; https://doi.org/10.1117/12.512542


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