19 November 2003 Configurable hardware implementation of H.264 decoder
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PixSil Technology's approach to hardware implementation of H.264 is highly modular. PixSil has designed its configurable hardware to be embedded within a System-on-chip (SOC). The processor manages most of the high-level frame management functions as well as set the parameters for control of the data stream. DMA engines direct the data stream to the hardware block. Many of the different profiles and levels of the H.264 standard are configurable by setting the desired parameters of the final system to the EDA software. Each block is selected to optimize the particular requirements of that level with the minimum amount of hardware. Clock speed may also be varied for power minimization. This concept is demonstrated using the Integer Transform Block of the H.264 algorithm stream. The paper illustrates how PixSil has designed the Integer Transform Block modules to meet the various throughput and I/O requirements for several of the different levels of H.264. Comparisons of area and power are made to a software-only implementation. Integration of the functional blocks completes the design of the full H.264 decoder. An SDRAM is the only external component required for PixSil Technology's FPGA/ASIC implementation of the decoder system.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
John T. Johl, John T. Johl, } "Configurable hardware implementation of H.264 decoder", Proc. SPIE 5203, Applications of Digital Image Processing XXVI, (19 November 2003); doi: 10.1117/12.508716; https://doi.org/10.1117/12.508716

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