24 December 2003 A radix-4 on-line division design and its application to networks of on-line modules
Author Affiliations +
On-line division is one of the slowest operations among the basic arithmetic operations and naturally becomes a bottleneck in networks of on-line modules that use it. A higher radix divider has a good potential to attain higher throughput than radix-2 dividers and therefore improve the overall throughput of networks where division is needed. The improvement in throughput when using radix 4 is not straightforward since several components of the divider become more complex than in the radix-2 case. Previously proposed radix-4 designs were based on operand pre-scaling to simplify the selection function and reduce the critical path delay, at the cost of more complexity in the algorithm conditions and operations, plus a variable on-line delay, which is a very unattractive feature when small precision values are used (usually the case for DSP). These designs include several phases for pre-scaling and actual division. This paper proposes a design approach based on overlapped replication that results in a radix-4 on-line division module with low algorithm complexity, single division phase, less restrictions to the input values, and a small and fixed on-line delay.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Alexandre F. Tenca, Ajay Shantilal, Mohammed Sinky, "A radix-4 on-line division design and its application to networks of on-line modules", Proc. SPIE 5205, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, (24 December 2003); doi: 10.1117/12.506455; https://doi.org/10.1117/12.506455


Design of a multi spectral TDICCD focal plane imaging and...
Proceedings of SPIE (November 18 2014)
Novel fast multiplier implemented using FPGA
Proceedings of SPIE (September 11 2015)
FPGA-based cavity simulator for Tesla test facility
Proceedings of SPIE (July 22 2004)
Malleable architecture generator for FPGA computing
Proceedings of SPIE (October 21 1996)
Partial reconfiguration-oriented design of logic controllers
Proceedings of SPIE (December 28 2007)

Back to Top