Flexible arithmetic and logic unit for multimedia processing

Murugappan Senthilvelan; Michael J. Schulte

doi:10.1117/12.506559

24 December 2003 Flexible arithmetic and logic unit for multimedia processing

Murugappan Senthilvelan, Michael J. Schulte

Proceedings Volume 5205, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII; (2003) https://doi.org/10.1117/12.506559
Event: Optical Science and Technology, SPIE's 48th Annual Meeting, 2003, San Diego, California, United States

Abstract

Novel arithmetic units are needed to achieve the cost, performance, power, and functionality requirements of emerging multimedia systems. This paper presents the design and implementation of a 64-bit arithmetic and logic unit (ALU) for multimedia processing. The 64-bit ALU supports subword-parallel processing by allowing one 64-bit, two 32-bit, four 16-bit, or eight 8-bit operations to be performed in parallel. In addition to conventional ALU operations, the ALU also supports several operations for enhanced multimedia processing including parallel compare, parallel average, parallel minimum, parallel maximum, and parallel shift and add. To efficiently implement a variety of multimedia applications, the ALU supports saturating and wrap-around arithmetic operations on unsigned and two's complement operands. This paper compares the area and delay of the 64-bit multimedia ALU to those of a more conventional 64-bit ALU.

Citation Download Citation

Murugappan Senthilvelan and Michael J. Schulte "Flexible arithmetic and logic unit for multimedia processing", Proc. SPIE 5205, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, (24 December 2003); https://doi.org/10.1117/12.506559

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