24 December 2003 Using truncated multipliers in DCT and IDCT hardware accelerators
Author Affiliations +
Abstract
Truncated multipliers offer significant improvements in area, delay, and power. However, little research has been done on their use in actual applications, probably due to concerns about the computational errors they introduce. This paper describes a software tool used for simulating the use of truncated multipliers in DCT and IDCT hardware accelerators. Images that have been compressed and decompressed by DCT and IDCT accelerators using truncated multipliers are presented. In accelerators based on Chen's algorithm (256 multiplies per 8 x 8 block for DCT, 224 multiplies per block for IDCT), there is no visible difference between images reconstructed using truncated multipliers with 55% of the multiplication matrix eliminated and images reconstructed using standard multipliers with the same operand lengths and intermediate precision.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
E. George Walters, E. George Walters, Mark G. Arnold, Mark G. Arnold, Michael J. Schulte, Michael J. Schulte, } "Using truncated multipliers in DCT and IDCT hardware accelerators", Proc. SPIE 5205, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, (24 December 2003); doi: 10.1117/12.506793; https://doi.org/10.1117/12.506793
PROCEEDINGS
12 PAGES


SHARE
RELATED CONTENT


Back to Top