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6 February 2004 Four-million-frame/s CMOS image sensor prototype with on-focal-plane 64-frame storage
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Abstract
An image sensor acquisition and readout circuit prototype, capable of 4 to 10 million frames/s and 79 dB (13 bits), RMS, dynamic range has been fabricated and tested. The 0.35 μm CMOS chip tests sensor and readout circuitry intended for applications such as accelerator-based radiography, where fast, brief, transient events can be captured with high resolution. It exhibits a unique combination of extremely high speeds and very wide dynamic range, as well as 64-frame analog storage on the focal plane array (FPA). Each pixel includes either a charge-integrating trans-impedance amplifier or a direct-integration source-follower front end, followed by an array of 64 sample capacitors and associated readout electronics. Flexible operation capabilities allows the acquisition of either 32 frames using correlated double sampling (CDS) at 4 M-frames/s, or 64 frames without CDS at 7 M-frames/s without any reduction in gain. Allowing a -3dB gain reduction, frame rates as high as 10.5 MHz can be achieved. CDS is performed by acquiring two samples per frame, one immediately after reset and one at the end of the integration period, followed by external subtraction of the two samples. Two samples at a time are read out in parallel when CDS is not required. A 200 by 200 μm pixel is implemented in order to mate an extended version to an existing back-illuminated hybrid photo-diode FPA.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Stuart Kleinfelder, Yandong Chen, Kris Kwiatkowski, and Ashish Shah "Four-million-frame/s CMOS image sensor prototype with on-focal-plane 64-frame storage", Proc. SPIE 5210, Ultrahigh- and High-Speed Photography, Photonics, and Videography, (6 February 2004); https://doi.org/10.1117/12.506196
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