2 September 2003 Lithography-independent fabrication of nano-MOS-transistors with W = 25 nm and L = 25 nm
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Proceedings Volume 5253, Fifth International Symposium on Instrumentation and Control Technology; (2003) https://doi.org/10.1117/12.521657
Event: Fifth International Symposium on Instrumentation and Control Technology, 2003, Beijing, China
Abstract
The 2001 update of the International Technology Roadmap for Semiconductors predicts a printed minimum MOS-transistor channel length of 13 nm for the year 2016, which results in a physical gate length of only 9 nm. The resolution of optical lithography still dramatically increases, but known and proved solutions for structure sizes significantly below 100 nm do not exist up to now. In this paper a new method for the fabrication of extremeley small MOS-transistors with a channel area down to W = 25 nm and L = 25 nm with low demands to the used lithography will be explained. It is based on our deposition and etchback technique which was used in earlier research to produce transistors with very small channel lengths down to 30 nm, while the channel width was not scaled. The used technique is full compatible to the CMOS-Process and therefore easily transferable to almost any other technology line. It results in an excellent homogeneity and reproducibility of the generated structure size.
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Christian Horst, Klaus T. Kallis, John T. Horstmann, Karl F. Goser, "Lithography-independent fabrication of nano-MOS-transistors with W = 25 nm and L = 25 nm", Proc. SPIE 5253, Fifth International Symposium on Instrumentation and Control Technology, (2 September 2003); doi: 10.1117/12.521657; https://doi.org/10.1117/12.521657
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