17 December 2003 Migration of 90-nm mask and wafer lithography learning into 130-nm mask production to improve performance and yield
Author Affiliations +
Abstract
Improvements in mask making techniques and metrology strategies have been required to satisfy the requirements of the 90nm technology node. With decreasing k1 and increasing MEF, critical dimension uniformity and defect specifications have faced severely tightened requirements. Many of the mask making process enhancements inspired by the 90nm node can be retrofitted into the 130nm node which improves mask quality as well as wafer-level performance. Mask critical dimension uniformity improvements directly impact wafer across chip linewidth variation which results in significantly improved chip performance. Specific examples of 130nm chip performance improvement will be discussed. Mask critical dimension and defect density improvements also result in improved mask yield and reduced mask costs. Driving 90nm mask process learning back into 130nm mask production significantly improves 130nm performance. Close interaction with the wafer lithography team allows focus on critical process window improvements for both the mask maker and wafer lithographer and allows rapid implementation of high-end process learning into older technologies.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Andrew Watts, Yiyang Jenny Wang, Jed Rankin, "Migration of 90-nm mask and wafer lithography learning into 130-nm mask production to improve performance and yield", Proc. SPIE 5256, 23rd Annual BACUS Symposium on Photomask Technology, (17 December 2003); doi: 10.1117/12.517877; https://doi.org/10.1117/12.517877
PROCEEDINGS
7 PAGES


SHARE
Back to Top