The chromeless phase lithography is a potential technology for low k1 optical image. Since the image quality is controlled by the phase interference, the phase error that results from mask processing becomes an issue. In the previous study, we have investigated the phase error effect and optimized the etching recipe by using the orthogonal DOE method. However, the 3D pattern profile is another critical factor, which affect the image intensity and needs to be clarified. In this paper, the through pitch L/S pattern with various profile angles were studied. Test patterns were measured, and verified by AFM, SEM, and metrology tools to get profile angles, phase values, and CD dimension. Simulation was used to predict the trend of process performance and analyze the impact on process control. The process windows for specific pattern profiles were also verified by wafer printing result. An optimized etching process and a set of spec recommendations for the CPL PSM was obtained.