30 March 2004 On-chip interconnect schemes for reconfigurable system-on-chip
Author Affiliations +
Abstract
On-chip communication architectures can have a great influence on the speed and area of System-on-Chip designs, and this influence is expected to be even more pronounced on reconfigurable System-on-Chip (rSoC) designs. To date, little research has been conducted on the performance implications of different on-chip communication architectures for rSoC designs. This paper motivates the need for such research and analyses current and proposed interconnect technologies for rSoC design. The paper also describes work in progress on implementation of a simple serial bus and a packet-switched network, as well as a methodology for quantitatively evaluating the performance of these interconnection structures in comparison to conventional buses.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Andy Sheng-Han Lee, Neil W. Bergmann, "On-chip interconnect schemes for reconfigurable system-on-chip", Proc. SPIE 5274, Microelectronics: Design, Technology, and Packaging, (30 March 2004); doi: 10.1117/12.523334; https://doi.org/10.1117/12.523334
PROCEEDINGS
12 PAGES


SHARE
KEYWORDS
Telecommunications

System on a chip

Logic

Network architectures

Standards development

Data communications

Field programmable gate arrays

RELATED CONTENT

Switched Multi-megabit Data Service
Proceedings of SPIE (January 15 1990)
Evolution of protocol testers from SMDS to B-ISDN
Proceedings of SPIE (October 15 1993)
PCS subscriber profile data and information requirements
Proceedings of SPIE (January 08 1996)
Clear-channel strategies for a scalable wide-area network
Proceedings of SPIE (December 01 1995)

Back to Top