30 March 2004 Quasi-3D modeling, design, and analysis of symmetric on-chip inductors in silicon-on-sapphire technology
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Abstract
A design and analysis of symmetric on-chip planar inductors are presented based in 0.5 μm silicon-on-sapphire CMOS process of Peregrine Semiconductor. Compared to conventional CMOS processes, an insulating thick sapphire (Al2O3) substrate enables higher quality factor inductors due to low energy loss in the substrate. In addition, symmetric cross-coupled configuration of identical asymmetric inductors of thick top metalization minimizes the insertion loss. Such differentially connected inductors are simulated on 2.5D electromagnetic field environment and a modeling method of quasi-3D structures is introduced for the metal strips. Maximum quality factor of 53.6 with 2.34 nH at 8.9 GHz is achieved by optimizing the symmetric circular inductors. This inductor is used in the design of a low power (0.42 mW) LC VCO operating at 5.8 GHz and exhibits a phase noise of -120.6 dBc/Hz at 3 MHz offset frequency.
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Wan-Chul Kong, Wan-Chul Kong, Said F. Al-Sarawi, Said F. Al-Sarawi, Cheng-Chew Lim, Cheng-Chew Lim, Louis Wong, Louis Wong, } "Quasi-3D modeling, design, and analysis of symmetric on-chip inductors in silicon-on-sapphire technology", Proc. SPIE 5274, Microelectronics: Design, Technology, and Packaging, (30 March 2004); doi: 10.1117/12.522049; https://doi.org/10.1117/12.522049
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