15 April 2004 Design and FPGA implementation for MAC layer of Ethernet PON
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Proceedings Volume 5282, Network Architectures, Management, and Applications; (2004) https://doi.org/10.1117/12.523176
Event: Asia-Pacific Optical and Wireless Communications, 2003, Wuhan, China
Abstract
Ethernet passive optical network (EPON), which represents the convergence of low-cost, high-bandwidth and supporting multiple services, appears to be one of the best candidates for the next-generation access network. The work of standardizing EPON as a solution for access network is still underway in the IEEE802.3ah Ethernet in the first mile (EFM) task force. The final release is expected in 2004. Up to now, there has been no standard application specific integrated circuit (ASIC) chip available which fulfills the functions of media access control (MAC) layer of EPON. The MAC layer in EPON system has many functions, such as point-to-point emulation (P2PE), Ethernet MAC functionality, multi-point control protocol (MPCP), network operation, administration and maintenance (OAM) and link security. To implement those functions mentioned above, an embedded real-time operating system (RTOS) and a flexible programmable logic device (PLD) with an embedded processor are used. The software and hardware functions in MAC layer are realized through programming embedded microprocessor and field programmable gate array(FPGA). Finally, some experimental results are given in this paper. The method stated here can provide a valuable reference for developing EPON MAC layer ASIC.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Zengxi Zhu, Rujian Lin, Jian Chen, Jiajun Ye, Xinqiao Chen, "Design and FPGA implementation for MAC layer of Ethernet PON", Proc. SPIE 5282, Network Architectures, Management, and Applications, (15 April 2004); doi: 10.1117/12.523176; https://doi.org/10.1117/12.523176
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