25 September 2003 An efficient parallel architecture for MPEG-4 zerotree encoder
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Proceedings Volume 5286, Third International Symposium on Multispectral Image Processing and Pattern Recognition; (2003) https://doi.org/10.1117/12.539061
Event: Third International Symposium on Multispectral Image Processing and Pattern Recognition, 2003, Beijing, China
Abstract
This paper presents a novel parallel hardware architecture for MPEG-4 zerotree encoder. Under the architecture, a parallel processing of multi bit-planes is fulfilled through a preprocess until and multi-encoding units. The preprocess unit consists of mainly a bit-not-and and a bit-or logic circuits. It ensures sufficiently that efficient encoding in each bit-plane is performed independently. Each encoding until uses a fast technique to assign symbols by taking advantage of MPEG-4 zerotree coding symbol alphabet, and to select valid data to output using a ZTR address buffer.
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Chao Xu, Chao Xu, Qing-Yun Shi, Qing-Yun Shi, } "An efficient parallel architecture for MPEG-4 zerotree encoder", Proc. SPIE 5286, Third International Symposium on Multispectral Image Processing and Pattern Recognition, (25 September 2003); doi: 10.1117/12.539061; https://doi.org/10.1117/12.539061
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