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18 December 2003 Design of high-performance coprocessor for color error diffusion
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Proceedings Volume 5293, Color Imaging IX: Processing, Hardcopy, and Applications; (2003) https://doi.org/10.1117/12.527238
Event: Electronic Imaging 2004, 2004, San Jose, California, United States
Abstract
In this paper, we present an architecture of a color halftoning coprocessor. The design is based on a software/hardware design approach in which the flexibility and adaptability of the programmable processor and the high performance, low power of ASIC design are utilized. We employ the concurrency and locality concepts in computer architecture to address the computational intensive and data intensive issues of the color halftoning algorithm. Both instruction parallelism and data parallelism are exploited to speed up the performance. In addition, the fine-grain and middle-grain instruction level parallelism (ILP) are utilized to accelerate the computation in the color error diffusion halftoning process.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Philip P. Dang "Design of high-performance coprocessor for color error diffusion", Proc. SPIE 5293, Color Imaging IX: Processing, Hardcopy, and Applications, (18 December 2003); https://doi.org/10.1117/12.527238
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