18 May 2004 High-performance low-power BinDCT coprocessor for wireless video applications
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This paper presents an efficient VLSI architecture and a low complexity implementation of BinDCT coprocessor for wireless video application. The coprocessor architecture was implemented in VHDL and was synthesized with 0.18 mm CMOS technology. The footprint of the 2-D BinDCT coprocessor, which includes memory buffer, is 0.1173 mm2. The BinDCT coprocessor can calculate video in CIF format at 30 frames per second at 5 MHz clock rate with 1.55-volt power supply. The BinDCT coprocessor dissipates 12.05 mW. With its fast transform, compact size and low power consumption, the BinDCT coprocessor is an excellent candidate for DCT-based wireless multimedia coding systems.
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Philip P. Dang, Philip P. Dang, Truong Q. Nguyen, Truong Q. Nguyen, Trac D. Tran, Trac D. Tran, } "High-performance low-power BinDCT coprocessor for wireless video applications", Proc. SPIE 5297, Real-Time Imaging VIII, (18 May 2004); doi: 10.1117/12.525128; https://doi.org/10.1117/12.525128


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