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28 May 2004 Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation
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Proceedings Volume 5298, Image Processing: Algorithms and Systems III; (2004) https://doi.org/10.1117/12.527235
Event: Electronic Imaging 2004, 2004, San Jose, California, United States
Abstract
We present a cellular pulse coupled neural network with adaptive weights and its analog VLSI implementation. The neural network operates on a scalar image feature, such as grey scale or the output of a spatial filter. It detects segments and marks them with synchronous pulses of the corresponding neurons. The network consists of integrate-and-fire neurons, which are coupled to their nearest neighbors via adaptive synaptic weights. Adaptation follows either one of two empirical rules. Both rules lead to spike grouping in wave like patterns. This synchronous activity binds groups of neurons and labels the corresponding image segments. Applications of the network also include feature preserving noise removal, image smoothing, and detection of bright and dark spots. The adaptation rules are insensitive for parameter deviations, mismatch and non-ideal approximation of the implied functions. That makes an analog VLSI implementation feasible. Simulations showed no significant differences in the synchronization properties between networks using the ideal adaptation rules and networks resembling implementation properties such as randomly distributed parameters and roughly implemented adaptation functions. A prototype is currently being designed and fabricated using an Infineon 130nm technology. It comprises a 128 × 128 neuron array, analog image memory, and an address event representation pulse output.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Juerg Schreiter, Ulrich Ramacher, Arne Heittmann, Daniel Matolin, and Rene Schuffny "Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation", Proc. SPIE 5298, Image Processing: Algorithms and Systems III, (28 May 2004); https://doi.org/10.1117/12.527235
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