7 June 2004 An ultralow-noise high-speed CMOS linescan sensor for scientific and industrial applications
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Abstract
This paper describes a 2048x1 linear image sensor implemented in a 0.35 μm 4M1P CMOS process that uses a low fixed pattern noise capacitive transimpedance amplifier (LFPN CTIA) pixel architecture. The pixel also includes circuitry for reducing 1/f noise, correlated double sampling, electronic shuttering, and a horizontal anti-blooming drain. High speed non-destructive readout of the sensor is achieved by using a hierarchical readout structure with two output ports. Using a JTAG interface the sensor can be programmed to operate in multiple readout modes. In the fastest readout mode, ROI, the sensor achieves 90Mpixel/sec (43.4Klines/sec) with 14e- RMS read noise. In the lowest noise mode, MRDI, with 13x oversampling of each pixel the sensor achieves 2.7Klines/sec with 1.2e- RMS read noise.
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Boyd A. Fowler, Boyd A. Fowler, Janusz Balicki, Janusz Balicki, Dana How, Dana How, Steve Mims, Steve Mims, John Canfield, John Canfield, Michael Godfrey, Michael Godfrey, } "An ultralow-noise high-speed CMOS linescan sensor for scientific and industrial applications", Proc. SPIE 5301, Sensors and Camera Systems for Scientific, Industrial, and Digital Photography Applications V, (7 June 2004); doi: 10.1117/12.526850; https://doi.org/10.1117/12.526850
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