Translator Disclaimer
18 January 2004 A half D1 MPEG-4 encoder on the BSP-15 DSP
Author Affiliations +
Proceedings Volume 5308, Visual Communications and Image Processing 2004; (2004) https://doi.org/10.1117/12.538252
Event: Electronic Imaging 2004, 2004, San Jose, California, United States
Abstract
In this paper, we present the work on implementation of a half-D1interlaced MPEG-4 encoder with Equator Technology DSP chip, BSP-15. The BSP-15 DSP consists mainly of a VLIW core, Co-processors, and media I/O interfaces. The encoder utilizes several BSP-15 functional blocks in parallel. In general, the VLIW performs pixel procesing that is computationally intensive. The VLx coprocessor completes variable length coding. Further parallelism is obtained by pre-loading data cache and doubling data buffers. Given the DSP processing power and real time requirements, a complexity control scheme is implemented. A frame-level quantization scheme with quality and rate control is employed. The current implementation for video at 30 fps consumes about 90% of the chip performance at a bit rate ~2Mbps.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Lulin Chen, Zhihai He, Chang Wen Chen, and Michael A. Isnardi "A half D1 MPEG-4 encoder on the BSP-15 DSP", Proc. SPIE 5308, Visual Communications and Image Processing 2004, (18 January 2004); https://doi.org/10.1117/12.538252
PROCEEDINGS
5 PAGES


SHARE
Advertisement
Advertisement
RELATED CONTENT

Heuristic dynamic complexity coding
Proceedings of SPIE (April 25 2008)
Generalized parallelization methodology for video coding
Proceedings of SPIE (December 28 1998)
DSP-based hardware for real-time video coding
Proceedings of SPIE (April 30 1992)

Back to Top