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19 April 2004 Low-power high-performance 2D transform coprocessor for H.264 video compression standard
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This paper presents a VLSI architecture and an efficient implementation of an embedded transform coprocessor for H.264 video compression standard. The proposed coprocessor was designed to work with an ARM946E-S processor. To enhance the performance, both data parallelism and pipelined architecture are utilized in the design. In this study, coprocessor was synthesized with 0.18 μm CMOS technology and its footprint is only 0.0838 mm2. Coprocessor can calculate 2-D transform for a macroblock in 30 clock cycles. The 2-D transform coprocessor dissipates 529 μW with 1.55-volt power supply at 10 MHz clock rate.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Philip P. Dang "Low-power high-performance 2D transform coprocessor for H.264 video compression standard", Proc. SPIE 5309, Embedded Processors for Multimedia and Communications, (19 April 2004);


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