Realization of vertical P+ wall through-wafer

J. L. Sanchez; E. Scheid; P. Austin; M. Breil; H. Carriere; Pascal Dubreuil; E. Imbernon; F. Rossel; B. Rousset

doi:10.1117/12.531533

30 December 2003 Realization of vertical P⁺ wall through-wafer

J. L. Sanchez, E. Scheid, P. Austin, M. Breil, H. Carriere, Pascal Dubreuil, E. Imbernon, F. Rossel, B. Rousset

Proceedings Volume 5342, Micromachining and Microfabrication Process Technology IX; (2003) https://doi.org/10.1117/12.531533
Event: Micromachining and Microfabrication, 2004, San Jose, California, United States

Abstract

P⁺ walls through wafer can be considered as key regions in the 3D architecture of new bi-directional current and voltage power integrated devices. Moreover, these P⁺ walls can be used as electrical vias in the design of microsystems, in order to make easier 3D packaging. In this paper, we demonstrate the possibility of fabricating these P⁺ walls combining the deep RIE of silicon and deposit of boron-doped polysilicon.

Citation Download Citation

J. L. Sanchez, E. Scheid, P. Austin, M. Breil, H. Carriere, Pascal Dubreuil, E. Imbernon, F. Rossel, and B. Rousset "Realization of vertical P⁺ wall through-wafer", Proc. SPIE 5342, Micromachining and Microfabrication Process Technology IX, (30 December 2003); https://doi.org/10.1117/12.531533

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