14 June 2004 Novel planarization and passivation in the integration of III-V semiconductor devices
Author Affiliations +
Abstract
III-V semiconductor devices typically use structures grown layer-by-layer and require passivation of sidewalls by vertical etching to reduce leakage current. The passivation is conventionally achieved by sealing the sidewalls using polymer and the polymer needs to be planarized by polymer etch-back method to device top for metal interconnection. It is very challenging to achieve perfect planarization needed for sidewalls of all the device layers including the top layer to be completely sealed. We introduce a novel hard-mask-assisted self-aligned planarization process that allows the polymer in 1-3 μm vicinity of the devices to be planarized perfectly to the top of devices. The hard-mask-assisted process also allows self-aligned via formation for metal interconnection to device top of μm size. The hard mask is removed to expose a very clean device top surface for depositing metals for low ohmic contact resistance metal interconnection. The process is robust because it is insensitive to device height difference, spin-on polymer thickness variation, and polymer etch non-uniformity. We have demonstrated high yield fabrication of monolithically integrated optical switch arrays with mesa diodes and waveguide electroabsorption modulators on InP substrate with yield > 90%, high breakdown voltage of > 15 Volts, and low ohmic contact resistance of 10-20 Ω.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jun-Fei Zheng, Peter Jesper Hanberg, Hilmi Volkan Demir, Vijit A. Sabnis, Onur Fidaner, James S. Harris, David A. B. Miller, "Novel planarization and passivation in the integration of III-V semiconductor devices", Proc. SPIE 5356, Optoelectronic Integrated Circuits VI, (14 June 2004); doi: 10.1117/12.529696; https://doi.org/10.1117/12.529696
PROCEEDINGS
11 PAGES


SHARE
RELATED CONTENT


Back to Top