A future maskless lithography system that replaces traditional masks with an array of electro-mechanical mirrors relies on a very high rate data interface to achieve the wafer throughputs comparable to today's optical lithography systems. In order to write one layer per minute in 45nm technology node, a throughput of 12Tb/s using 5-bit grayscale data is needed. With EUV light source flash rates limite to below 10kHz, 240 million 1μm x 1μm micromirrors have to be integrated on the writer chip, each driven with 32 possible voltage levels.
This paper explores the system design for various wafer throughputs, with or without data compression. In particular, the design tradeoffs for the mirror interface datapath, implemented on the same silicon die with the writers are discussed. The design of the digita-to-analog converters (DACs) that compensate for the nonlinearity of the mirror transfer function and fit into the required datapath pitch is presented. Extrapolated data from the designs in 0.13μm CMOS technology indicate that DACs will likely limit the throughput to about 30 wafers per hour in 45nm node.