Improved overlay metrology device correlation on 90-nm logic processes

Atsushi Ueno; Kouichirou Tsujita; Hiroyuki Kurita; Yasuhisa Iwata; Mark Ghinovker; Jorge M. Poplawski; Elyakim Kassel; Mike E. Adel

doi:10.1117/12.534522

24 May 2004 Improved overlay metrology device correlation on 90-nm logic processes

Atsushi Ueno, Kouichirou Tsujita, Hiroyuki Kurita, Yasuhisa Iwata, Mark Ghinovker, Jorge M. Poplawski, Elyakim Kassel, Mike E. Adel

Author Affiliations +

Proceedings Volume 5375, Metrology, Inspection, and Process Control for Microlithography XVIII; (2004) https://doi.org/10.1117/12.534522
Event: Microlithography 2004, 2004, Santa Clara, California, United States

Abstract

Isolated and dense patterns were formed at process layers from gate through to back-end on wafers using a 90 nm logic device process utilizing ArF lithography under various lithography conditions. Pattern placement errors (PPE) between AIM grating and BiB marks were characterized for line widths varying from 1000nm to 140nm. As pattern size was reduced, overlay discrepancies became larger, a tendency which was confirmed by optical simulation with simple coma aberration. Furthermore, incorporating such small patterns into conventional marks resulted in significant degradation in metrology performance while performance on small pattern segmented grating marks was excellent. Finally, the data also show good correlation between the grating mark and specialized design rule feature SEM marks, with poorer correlation between conventional mark and SEM mark confirming that new grating mark significantly improves overlay metrology correlation with device patterns.

Citation Download Citation

Atsushi Ueno, Kouichirou Tsujita, Hiroyuki Kurita, Yasuhisa Iwata, Mark Ghinovker, Jorge M. Poplawski, Elyakim Kassel, and Mike E. Adel "Improved overlay metrology device correlation on 90-nm logic processes", Proc. SPIE 5375, Metrology, Inspection, and Process Control for Microlithography XVIII, (24 May 2004); https://doi.org/10.1117/12.534522

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