Tapered resist profiles have been found to cause a deterimental effect on the overlay measurement capability, affecting lithography processes which utilize thick implant resist. Particularly, for resist thicknesses greater than 1.5 μm, the systematical contribution to the overlay error becomes predominant. In CMOS manufacturing, these resist types are being used mainly for high energy well implants. As design rules progressively shrink, the overlay requirements are getting tighter, such that the limits of the process capability are reached. Since the resist thickness cannot be reduced due to the requirements of the implant process, it becomes inevitable to reduce the systematical overlay error for the litho process involving thick resists. The following analysis concentrates on the tapers of overlay marks printed on thick i-line positive resists. Conventionally, overlay between two litho layers is measured from box in box marks with respect to a reference layer where the statistical shift between the boxes is expected to provide the biggest source of residuals. We observed however that an even bigger error could be introduced by an unevenness of the i-line resist tapers, adding asymmetrical chip magnification. The inclination of these tapers depends on the proximity and surface of the surrounding features and stack variations. We show that by adjusting soft and hard bake temperatures and times, tapers can be significantly reduced and thereby the overlay performance was greatly improved.