24 May 2004 Test of a new sub-90-nm DR overlay mark for DRAM production
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An improved overlay mark design was applied in high end semiconductor manufacturing to increase the total overlay measurement accuracy with respect to the standard box-in-box target. A comprehensive study has been conducted on the basis of selected front-end and back-end DRAM layers (short loop) to characterize contributors to overlay error. This analysis is necessary to keep within shrinking overlay budget requirements.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Stefan Gruss, Stefan Gruss, Ansgar Teipel, Ansgar Teipel, Carsten Fuelber, Carsten Fuelber, Elyakim Kassel, Elyakim Kassel, Mike Adel, Mike Adel, Mark Ghinovker, Mark Ghinovker, Pavel Izikson, Pavel Izikson, } "Test of a new sub-90-nm DR overlay mark for DRAM production", Proc. SPIE 5375, Metrology, Inspection, and Process Control for Microlithography XVIII, (24 May 2004); doi: 10.1117/12.534518; https://doi.org/10.1117/12.534518

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