14 May 2004 A planarization process for multilayer lithography applications
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Abstract
Multi-layer lithography processes have been introduced to fabricate very fine structures over a topographic surface for advanced semiconductor device production. The first layer formed on the topographic surface is the planarization layer to provide surface planarity for additional thin layer(s) of material. Such materials could be a photoresist, a hardmask, or both with uniform film thickness for the lithography step to image the structures. However, the large size and distribution variation of the topography structures across the substrate surface have a major impact on the performance of the lithography processes. A new planarization process, contact planarization (CP), has been introduced to improve thickness uniformity and to provide global surface planarity for multi-layer lithography applications. This study focuses on planarizing an experimental organic 193-nm BARC layer on via wafers to minimize iso-dense film thickness bias and provide improved global surface planarity for the bilayer photolithography process. In addition, minimum thickness bias improves control of downstream processes such as plasma etching. This paper will discuss this unique planarization process and its performance with various thicknesses of the experimental 193-nm BARC on via wafers. The photolithography performance of the material and process will be discussed.
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Wu-Sheng Shih, Wu-Sheng Shih, Charles J. Neef, Charles J. Neef, Mark G. Daffron, Mark G. Daffron, "A planarization process for multilayer lithography applications", Proc. SPIE 5376, Advances in Resist Technology and Processing XXI, (14 May 2004); doi: 10.1117/12.535303; https://doi.org/10.1117/12.535303
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