Effect of line-edge roughness (LER) and line-width roughness (LWR) on sub-100 nm device performance

Ji-Young Lee; Jangho Shin; Hyun-Woo Kim; Sang-Gyun Woo; Han-Ku Cho; Woo-Sung Han; Joo-Tae Moon

doi:10.1117/12.534926

14 May 2004 Effect of line-edge roughness (LER) and line-width roughness (LWR) on sub-100-nm device performance

Ji-Young Lee, Jangho Shin, Hyun-Woo Kim, Sang-Gyun Woo, Han-Ku Cho, Woo-Sung Han, Joo-Tae Moon

Author Affiliations +

Proceedings Volume 5376, Advances in Resist Technology and Processing XXI; (2004) https://doi.org/10.1117/12.534926
Event: Microlithography 2004, 2004, Santa Clara, California, United States

Abstract

ArF lithography is essential to develop a sub-100 nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER/LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER/LWR to device performance so that the reasonable control range of LER/LWR can be defined. To implement the experiment, 80 nm node of single NMOS transistors were fabricated, which had various range of gate length, width, and LER/LWR. The amount of LER/LWR could be successfully controlled by applying different resist materials, defocus, and over etch time. Experimental results show that leakage current is significantly increased when LWR is greater than 10 nm. In addition, it is observed that both threshold voltage and on-off current variation get increased exponentially as gate width decreases.

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Ji-Young Lee, Jangho Shin, Hyun-Woo Kim, Sang-Gyun Woo, Han-Ku Cho, Woo-Sung Han, and Joo-Tae Moon "Effect of line-edge roughness (LER) and line-width roughness (LWR) on sub-100-nm device performance", Proc. SPIE 5376, Advances in Resist Technology and Processing XXI, (14 May 2004); https://doi.org/10.1117/12.534926

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