ArF lithography is essential to develop a sub-100 nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER/LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER/LWR to device performance so that the reasonable control range of LER/LWR can be defined. To implement the experiment, 80 nm node of single NMOS transistors were fabricated, which had various range of gate length, width, and LER/LWR. The amount of LER/LWR could be successfully controlled by applying different resist materials, defocus, and over etch time. Experimental results show that leakage current is significantly increased when LWR is greater than 10 nm. In addition, it is observed that both threshold voltage and on-off current variation get increased exponentially as gate width decreases.