Over the past year interest in DFM has exploded in the semiconductor industry, and this despite the lack of a uniform working definition. The origin of this surge is shown to be related to three converging trends: increased design cost, shortened product lifetimes, and lower manufacturing yields for 130 nm technologies versus previous generations. A comparison to other industries reveals the distinct challenges attendant to semiconductor DFM and highlights the unique risks, which often necessitate non-intuitive solutions. Finally, the case is made to view DFM as a woven throughout the physical design flow, from cell design to mask data prep.

For the last several years, Resolution Enhancement Technologies (RETs) have helped make it possible for lithographers to stay on the path set for them by Goordon Moore. Though seldom discussed in detail, these RETs have a real cost in terms of data file size, computation times, complexity of metrology and inspection, licenses fees, manpower and delay. The International Sematech Cost of Ownership (CoO) analysis can be used to estimate the impact of RETs on overall Lithography CoO and on the cost per modern semiconductor wafer, which appears to be around $10/ RET level for a high-volume ASIC case.

The implementation of alternating phase shifted mask lithography for the poly-conductor level of IBM's leading edge 65nm microprocessor is described. Very broad and 'resolution-enhancement-technology generic' design rules, referred to as radical design restrictions, are demonstrated to be key enablers of alternating phase shifted mask design. The benefit of these radical design restrictions over conventional design rules and other alternating phase shifted mask design approaches is detailed for key aspects of the design flow.

The extension of optical lithography to ever deeper sub-wavelength feature sizes has led to an alarming increase in photo-mask complexity and associated cost. Changes in design philosophy can play a key role in mitigating this trend. We propose the introduction of a new optimization cycle early in the physical design process based on minimizing pattern complexity. We study the use of a pattern complexity metric based on Fourier coding to accomplish such an optimization. The ultimate goal is simplification of resolution enhancement technology (RET) methods required for a given design and the generation of a correspondingly simpler and more cost effective mask set.

In this paper, we discuss the results from a test chip that demonstrate the manufacturability and integration-worthiness of the X Architecture at the 90-nm technology node. We discuss how a collaborative effort between the design and chip making communities used the current generation of mask, lithography, wafer processing, inspection and metrology equipment to create 45 degree wires in typical metal pitches for the upper layers on a 90-nm device in a production environment. Cadence Design Systems created the test structure design and chip validation tools for the project. Canon’s KrF ES3 and ArF AS2 scanners were used for the lithography. Applied Materials used its interconnect fabrication technologies to produce the multilayer copper, low-k interconnect on 300-mm wafers. The results were confirmed for critical dimension and defect levels using Applied Materials’ wafer inspection and metrology systems.

The X Architecture is a new way of orienting the interconnect on an integrated circuit using diagonal pathways, as well as the traditional right-angle, or Manhattan, configuration. By enabling designs with significantly less wire and fewer vias, the X Architecture can provide substantial improvements in chip performance, power consumption and cost. Members of the X Initiative semiconductor supply chain consortium have demonstrated the production worthiness of the X Architecture at the 130-nm and 90-nm process technology nodes. This paper presents an assessment of the manufacturing readiness of the X Architecture for the 65-nm technology node. The extent to which current production capabilities in mask writing, lithography, wafer processing, inspection and metrology can be used is discussed using the results from a 65-nm test chip. The project was a collaborative effort amongst a number of companies in the IC fabrication supply chain. Applied Materials fabricated the 65-nm X Architecture test chip at its Maydan Technology Center and leveraged the technology of other X Initiative members. Cadence Design Systems provided the test structure design and chip validation tools, Dai Nippon Printing produced the masks and Canon’s imaging system was employed for the photolithography.

The layout strategies of standard cells with regularly-placed contacts and gates are studied. The regular placement enables more effective use of resolution enhancement technologies, which in turn allows a reduction of critical dimensions. Although regular placement of contacts and gates adds restrictions during cell layout, the overall circuit area can be made smaller and the number of extra masks and exposures can be kept to the lowest by careful selection of the grid pitch, using template-trim lithography method, allowing random contact placement in the vertical direction, and using rectangular rather than square contacts. Three different fabrication-friendly layouts are compared in this study. The average area change of 64 standard cells in a 130nm library range from -4.2% to -1.2% with the 3 fabrication-friendly layout approaches. The area change of 5 test circuits using the 3 approaches range from -5.4% to +2.6%. Power consumption and intrinsic delay also improve with the decrease in circuits area, which is verified with the examination results.

The use of subresolution assist features (SRAFs) in the photo mask is one of resolution enhancement techniques in photolithography, which can minimize linewidth variation caused by proximity effect. However, the process latitude with SRAFs through various pitches is not uniform. From the point of view of lithography, pitches with low process latitude, called forbidden areas, should be avoided. These forbidden areas exist often in the layout after routing since they are larger than the minimum clearance required in the design rules. In this paper, a pitch optimization method applied in the post-routing phase is proposed to avoid the forbidden areas. Experimental data of lithography techniques and geometric constraints from the layout are formulated into a constrained quadratic optimization problem. By using the spacing technique, wire segments in the affected area are adjusted to their new locations obtained from solving the optimization problem by quadratic programming. Examples show that the proposed method can avoid most forbidden areas in the layout after normal routing.

Layout test patterns are being pursued that are more sensitive than circuit patterns in detecting and quantifying residual processing effects. These patterns permit the rapid searching of layouts for the locations of worst-case process impacts, and may facilitate layout compensation at OPC speeds. These patterns have been taped-out along with snippets of circuits in preparation for experimental verification of the ability to link residual process effects to electronic design. The collection includes pattern-and-probe-based targets for measuring aberrations, illumination non-uniformity and etch-depth errors in phase-shifting masks, plasma etching with loading effects related to area and perimeter factors, and patterns for CMP orientation and feature proximity. The goal is to use these test patterns to develop maximum lateral impact functions for each individual process effect for use in fast-CAD techniques capable of inspecting large layouts.

Deep sub-wavelength optical imaging distorts the shape of MOSFET channel on silicon due to proximity and refraction. As a result, channel area is no longer rectangular, i.e., represented by the single channel length and width (LxW) for device simulations, but by an L(W) distribution. This distribution would differ across the optical proximity correction (OPC) and photo process windows, possibly exceeding the typical 10% CD variation entitlement. While one can expect that the process-related L(W) would impact MOSFET electrical properties, its circuit consequences have not been addressed in the typical simulation flow. In this work, we examine the impact of non-rectangular channel geometry on the basic MOSFET parameters such as the drive and leakage current. We then create models of the resulting inverter characteristics and of the static noise margin of an SRAM cell. In the process, we show how to simulate MOSFET gate shape for the different OPC and lithography options and identify the channel sections responsible for the parametric variations. Finally, we calculate electrical characteristics of SRAM cell based on the discretized representation of individual MOSFETs, showing how the distortion of channel geometry would degrade cell performance.

Layout engineering is the link in the design flow with the highest degree of freedom for manufacturability optimization. Generating correct lithography-ready mask data as part of layout design would significantly shorten product’s time to market. Until recently, however, a layout designer has no way of evaluating the manufacturability beyond design rules. In this paper, we propose to integrate a comprehensive manufacturability preview capability into the layout design environment. Based on the feedback from process simulation, a correct by construction approach for generating manufacturing friendly layout is proposed. It consists of selective mask optimization and process weak spot detection. We demonstrate the advantage of correct process construction using MOSIS standard cell library and discuss its future applications.

We describe a numerical model for chip level lithography variability analysis. Gate level critical dimensions are adjusted based on lithographic variability simulations and these perturbed gate lengths are input to a chip timing analyzer. Statistical modeling studies highlight the interaction between lithography variability and chip timing performance including the role of lithography error correlation length, optical proximity effect residuals, exposure system imperfections and photomask errors. Understanding these relationships is a critical building block for lithographic error tolerancing, design manufacturability improvement and lithography limited yield enhancements on integrated circuits for which timing is a key performance metric.

With downscaling of dimensions, essential challenges on layout printability significantly increase. The design rule cannot be shrunk with linearity any more. Historically, in the early development stage, simple test patterns like snake/comb or border/borderless via chains were used for identifying design and process issues electrically. However it is unclear how much these patterns represent the sensitive patterns for the real critical failures. The lack of these kinds of critical patterns would always cause yield problems in the volume production. In this paper, we show the result of evaluating 65-nm BEOL process by using the test patterns that can cover critical layout situations. Especially, it was focused on the line end via hole, which is believed to cause the systematic yield degradation. The key steps in our process/design decomposition methodology are design attribute and process space analysis. By exploring the process space for a given design, the method allows to find the most challenging patterns to print due to various process issues. The test patterns were generated from critical pattern extracted from standard cells library by considering our preliminary opc and mask design flow. Simulation of all test patterns are performed to ensure that DOE range is sufficient to cover the entire process/design space. These patterns are generated from the 65nm node ground design rule. It used a size of 90nm as metal minimum width and space, and a size of 100nm for fixed via hole diameter. It was confirmed by simulations that all the test pattern represent for the original design on each module process/design space. All the test patterns were measured by the standard parametric e-test setup. The amount of line end pull back can be inferred from the via resistance, and the amount of line end widening can be inferred from the leakage current between via chains and neighboring lines. Thus the meaningful information about the OPC and litho process can be obtained quickly without extensive use of SEM measurements. More than 200 test patterns considering logic randomness were designed and fabricated by using 65-nm node BEOL process. We found that 50nm or more line extension is necessary to suppress the pull back issue caused by the defocus effect. To prevent the metal short of the isolated pattern next to or surrounding by the wide metal, the minimum space with wide neighboring metal was defined. Using this methodology, our 65-nm design rule has been successfully evaluated and optimized.

Mixed-signal communication circuits are becoming a very common component of systems-on-a-chip as part of modern communication systems. The implementation of DFM and DFT methodologies is critical to enhance communication across the tape-out barrier critical for these circuits. We present a manufacturing-aware design methodology specifically targeting integrated communication circuits in systems-on-a-chip (SoC). The key principle behind the methodology is that flexible design methods which can effectively adjust a design’s power consumption and functionality to its application can also provide critical reductions in manufacturing-induced design risk. The methodology is based on the following four techniques: goal-based design that directly relates top level goals with low level manufacturing-dependent parameters; semi-custom voltage-island physical design techniques; adaptive architecture design; and intelligent on-line at-speed monitoring and problem determination techniques. We describe these four methodology features, and illustrate them on a multi-protocol CMOS 3.2 Gbits/second low-power serial communications core. The presented data shows how this methodology results in better and more cost-effective adaptability of the design to manufacturing and post-manufacturing conditions, thereby improving turnaround time, yield, and overall profit.

Design for manufacturability ( DfM ) flow consisting of a new lithography design approach at the design rule definition stage and manufacturability check at physical layout stage is proposed to clean up hot spots and guarantee the final layouts to be free of hot spots under low-k1 lithography condition. At the initial development stage, design rules ( DRs ), resolution enhancement technique ( RET ) and optical proximity correction ( OPC ) methods and critical dimension ( CD ) target and specification are determined by the new lithography design approach to reduce hot spots next-generation’s tentative layout made by the compactor. At the physical layout stage, a manufacturability check ( MC ) is essential to wipe out hot spots resulted from immaturity of DRs and process parameters fixed at the initial development stage by making three feedback approaches: the refinement of design rule, the repair of hot spots by designers and the refinement of OPC parameters and/or methods. Also, an alternative of layout modification or OPC improvement for cleaning hot spots are cleared by categorization of CD variation induced by some dose and focus conditions and an error of CD average for the target pattern. The proposed DfM flow is found to be highly effective for the robust pattern formation under the low-k1 lithography condition.

Tight ACLV control has become increasingly diffcult due to the diminishing process constant, K1. Focus variation and pitch variation are two major systematic components of ACLV. In this paper, we demonstrate these systematic effects and propose a design flow which exploits the systematic effect. We demonstrate the systematic ACLV by showing a Bossung plot for a nominal 90nm technology node. The plot is generated by simulation with lithographic parameters closely resembling a production technology node. Traditionally, tight CD control is achieved by sophisticated RET such as OPC, SRAF, AltPSM and more recently the Dense Template Design. The CD variation is specified in the design manual and the circuit designs will ensure functionality by building in enough margin to account for the variability. Even though, the systematic components of CD variation are understood, they have always been considered together with other random components as being random. This approach has left design performance on the table. We propose a holistic design flow by integrating the technology development process, design process and the manufacturing process. This holistic approach is aiming to tame the systematic through-pitch and through-focus CD variation. We quantify the design timing benefit using this approach by circuit design experiments. Results of our experiments show that timing uncertainty can be reduced by up to 30%. We also discuss other possibilities which are infeasible to carry out in traditional approach with silos of technology development, design and manufacturing.

The ever-increasing complexity of integrated circuits and their enabling process technology has accelerated the increase in data volume of post-RET data which is input to the photomask manufacturing industry. OASIS - the new stream format that has been developed by a working group under the sponsorship of the SEMI Data Path Task Force enables the representation of IC layout data in a much more compact form than GDSII and facilitates the incorporation of hierarchical data into the mask-making infrastructure. OASIS achieves on average a >10x reduction in file size compared to GDSII files and structures the data in a way, which allows a straightforward translation from a hierarchical format to the required flat mask perspective. Owing to the efficiency in representing the data, OASIS files are smaller than commonly used flat exchange formats - like MEBES, thus enabling an efficient hierarchical data flow both from the processing as well as the file handling prospective. The implementation of OASIS into post-tapeout data flows will be discussed and experimental results on OASIS-based data preparation flows will be shown.

The patterning of logic layouts for the 65nm and subsequent device generations will require the implementation of new capabilities in process control, optical proximity correction (OPC), resolution enhancement technique (RET) complexity, and lithography-design interactions. Many of the methods used to implement and verify these complex interactions can be described as design for manufacturability (DFM) techniques. In this paper we review a wide range of existing non-lithographic and lithographic DFM techniques in the semiconductor industry. We also analyze existing product designs for DFM technique implementation potential and propose new design methods for improving lithographic capability.

As the industry is targeting the sub-100nm nodes the pressure on the data path and tapeout flow is growing. Design complexity and increased deployment of resolution enhancement techniques (RET) result in rapidly growing file sizes, which impacts the data preparation time, especially for variable-shaped beam mask writing machines. Properties of the incoming layout - hierarchy, grid and aggressiveness of the RET are the main factors. Tuning the OPC without compromising the lithographic performance while achieving the shortest processing time is the target. The study investigates the impact of OPC setup with a focus on using the functional intent of the design to influence the aggressiveness of the correction. The correlation to the performance parameters for the mask data preparation and mask writing, like run-time, file size, shot count and small figures, will be reported.

One of the most compute intensive dataprep operations for 90nm PC level is the model-based optical proximity correction (MBOPC). The running time and output data size are growing unacceptably, particularly for ASICs and designs containing large macros built out of library cells (books). The reason for this growth is that the region-of-interest for MBOPC is approximately 600nm, which means that most library cells “see” interactions with adjacent books in the same row and also in adjacent rows. In this paper, we investigate the merits of doing cellwise MBOPC. In its simplest form, the approach is to perform dataprep for each cell once per cell definition rather than once per placement. By inspection, this will reduce the computation time and output data size by a factor of P/D, where P is the number of book placements (100s to millions) and D is the number of book definitions. Our preliminary finding indicates that there is negligible difference between nominal CD for cellwise corrected cells and chipwise corrected cells. We will present our finding in terms of average CD and contact coverage, as well as runtime reduction.

Under low-k₁ patterning constraints, it has been a challenge for the lithography process to meet the aggressive IC design rule requirements for the 90nm and the upcoming 65nm nodes. From the imaging perspective, we see the geometric design rules are largely governed by numerical aperture (NA), illumination settings, and OPC for any resolution enhancement technique (RET) applied mask. We report a case study of exploring a set of process feasible design rule criteria based on a state-of-the-art μProcessor chip that contains three different styles of circuit design - standard library cell (SLC), random logic (RML), and SRAM. To keep the packing density higher for SRAM, the critical criteria for design rules involve achievable minimum pitch, sufficient area of contact-landing pad, minimum line end shortening (LES) to ensure poly endcap, and preferably to have optimum pitch for the placement of Scattering Bars (SB). For RML, the goal is to achieve the printing of ever smaller critical dimension (CD) with a greater CD uniformity control. The SLC should be designed to be comparable with both RML and SRAM devices. Hence, the design rule constraints for CD, space, line end, minimum pitch, and SB placement for SLC cell is critically confined. Unlike the traditional method of assuming a linear scaling for the design rule set, we explore achievable design rule criteria for very low k₁ imaging by simultaneously optimizing NA, illumination settings, and OPC (for the optimum placement of SB) for a calibrated process. This is done by analyzing the CD control and the maximum overlapped process window for critical lines, spaces, line ends, and with the respective k₁ factor for the three types of circuits. For 90nm node with k₁ as low as 0.36, a feasible set of design rules for the μProcessor chip can be obtained using 6% attPSM with 6% exposure latitude at 400nm of overlapped depth of focus. Using the similar approach for the scaled down 65nm 6% attPSM, it resulted inadequate process latitude under a set of desired design rule constraints for critical pitch, CD, line end, minimum space, and SB placement. Hence for 65nm case, a CPL mask was used instead, as CPL (100% transmission) has the inherent capability of printing very thin line. The critical design rule criteria for SRAM, RML and SLC were revisited to ensure a large enough process margin.

The rapidly escalating complexity of resolution enhancement techniques (RET), now commonplace in leading edge lithography, requires accurate verification to avoid yield and performance problems on the patterned wafers. Model-based verification techniques that have been derived from optical proximity correction (OPC) obtain the required checking speed from sparse sampling of the layout at discrete evaluation points along the edges of layout patterns. This sparse sampling allows accurately calibrated models to be used for full chip checking applications. However, there is a demonstrated risk of missing significant patterning errors due to the sparse and edge-centric sampling of the layout. Grid-based simulation approaches which calculate the image on a fine grid over the entire layout space accurately detect patterning problems anywhere in the layout, but can be executed at reasonable runtimes for aerial image models only. The challenge for full-chip model-based verification of RET-enhanced layouts is, therefore, a trade-off between sparse, edge-centric simulation using accurate models versus simulations using approximate models over the entire layout space. This paper presents an approach, termed contourIFV, that has been demonstrated to overcome the aforementioned problems and has been shown to provide significant value in the verification of the RET and OPC prescription.

IC layouts are typically defined with simple shapes such as rectangles and 45° triangles. Fundamental limitations in the imaging process unavoidably prevent the exact rendering of these shapes on the wafer, and this necessitates an interpretation of what should appear on silicon. For example, an OPC tool must interpret a square corner as something more rounded, otherwise the pursuit of the ideal shape may lead to bridging and/or Mask Rule Check (MRC) violations. A solution to this is to move the target points for Optical Proximity Correction (OPC) off from the GDS edges and onto mathematically described curves inscribed within the corners of the design polygon and use these as the target for OPC correction. Suitable values for the radius of these curves depend on the model used, the geometry they are applied to, and the requirements of the device the shape builds. An uncorrected square corner gives a printed contour whose radius of curvature, nearest the design corner, provides a target radius for a low impact OPC correction. Line ends, right angled bends in tracks and end caps all need separate optimization in terms of the best radius of target curve to use. By understanding whether the design priority is for CD control (such as poly gate) or for positional accuracy (such as contact enclosure) the OPC correction parameters and final target shape can be modified in such a way to best realize these interpreted goals.

We present design-for-manufacturing and yield (DfM/DfY) results on SRAM of the 65-nm node by connecting knowledge of device performance with that of lithographic optical enhancement techniques. Of special interest was the lithographic quality of line-ends and gates, the former being the most critical for yield and manufacturing control. Scalability towards lower technology nodes was also part of the choice. All these considerations led to the choice of alternating-aperture phase-shift lithography as optimal reticle-enhancement technique. Predictions from simulations were verified on the wafer for SRAM cells of multiple geometry contexts, misalignment was included, and the illuminator was optimized.

The footprint of multi-transistor memory cell is limited by a complex connectivity layout. Depending on the architecture, the interconnect layers might be a hindrance in scaling the cell. This limitation is a result of the need for having multiple contacts to active or gate regions within small cell area as well as by the tight overlay requirements between these contacts and the overlaying metal. Minimum chrome line (i.e., contact space) CD of an attenuated phase shift mask used for printing these contacts as well as the mask and stepper alignment tolerances scale down slower than required by the technology roadmap. Moreover, the novel memory cell applications call for the increased cell complexity. In this work, we discuss how a combination of a new single damascene and self-aligned dual-damascene processes impact the area of a 6-Transistor Double-Wordline SRAM cell. We first identified the optimal cell architecture, followed by developing a unique interconnect scheme. In consequence, the area of the cell was reduced by as much as 25% within the 90 nm technology node. The new interconnect layer has been enabled at the expense of one additional mask.

We have previously presented the smallest and fastest 6 Transistor (6T)-Static Random Access Memories (SRAM) bitcells for System-on-Chip (SoC) high-density (HD) memories in 0.18 μm and 0.13 μm technologies. Our 1.87 μm² 6TSRAM bitcell with cell current of 47 μA and industry lowest soft error rate (0.35 FIT/Kbit) is used to assemble memory blocks embedded into SoC designs in 0.13 μm process technology. Excellent performance is achieved at a low overall cost, as our bitcells are based on standard CMOS process and demonstrate high yields in manufacturing. This paper discusses our methodology of embedded SRAM bitcell design. The key aspects of our approach are: 1) judicious selection of tightest achievable yet manufacturable design rules to build the cell; 2) compatibility with standard Optical Proximity Correction (OPC) flow; 3) use of parametric testing and yield analysis to achieve excellent design robustness and manufacturability. A thorough understanding of process limitations, particularly those related to photolithography was critical to the successful design and manufacturing of our aggressive, yet robust SRAM bitcells. The patterning of critical layers, such as diffusion, poly gate, contact and metal 1 has profound implications on functionality, electrical performance and manufacturability of memories. We have conducted the development of SRAM bitcells using two approaches for OPC: a) "manual’ OPC, wherein the bitcell layout of each of the critical layers is achieved using iterative improvement of layout & aerial image simulation and b) automated OPC-compatible design, wherein the drawn bitcell layout becomes a subject of a full chip OPC. While manual-OPC remains a popular option, automated OPC-compatible bitcell design is very attractive, as it does not require additional development costs to achieve fab-to-fab portability. In both cases we have obtained good results with respect to patterning of the critical layers, electrical performance of the bitcell and memory yields. A critical part of our memory technology development effort is the design of memory-specific test structures that are used for: a) verifying electrical characteristics of SRAM transistors and b) confirming the robustness of the design rules used within the SRAM cell. In addition to electrical test structures, we have a fully functional SRAM test chip called RAMPCM that is composed of sub-blocks each designated to evaluate the robustness of a specific critical design rule used within the bitcells. The results from the electrical testing and RAMPCM yield analysis are used to identify opportunities for improvements in the layout design. The paper will also suggest some techniques that can result in more design friendly OPC solutions. Our work indicates that future IC designs can benefit from an automated OPC tool that can intelligently handle layout modifications according to design priorities.

In sub-wavelength lithography, light field Alt-PSM (Alternating Phase Shifting Mask) is an essential technology for poly layer printability. In a standard cell based design, the problem of obtaining Alt-PSM compliance for an individual cell layout has been solved well [3]. However, placing Alt-PSM compliant cells together can not guarantee Alt-PSM compliance of the entire chip/block layout due to phase interactions among adjacent cells. A simple solution to this Alt-PSM composability problem is to wrap blank area around each cell, which is very inefficient on chip area usage. In this paper, we formulate the composability problem as a graph model and propose a polynomial time optimal algorithm to achieve Alt-PSM composability with the least impact on cell layout.

A method to fabricate a very thin channel body Fin-FET and Tri-gate MOSFET is presented. 8% Attenuated Phase-shift mask (APSM) and single phase chrome-less mask (CLM) techniques are evaluated to pattern fins in sub-50 nm regime using KrF lithography scanner with a maximum numerical aperture of 0.68. Some of the issues of single phase CLM technique with respect to fin patterning are highlighted. Dual Exposure With Shift (DEWS)’ is introduced to pattern gate lines down to 80 nm using binary mask.

In recent years it has become apparent that power supply voltage drops during circuit operation can result in abnormal operations in ULSI semiconductor chips. To resolve this problem, we have inserted a decoupling capacitor into our products. This paper presents insertion methods for internal decoupling capacitors to reduce the voltage-drop problem in chemical mechanical polish (CMP) and ultra large-scale integration (ULSI). A decoupling capacitor has a high pattern density leading to high density locally in the domain in which it is placed. Consequently, arranging conventional decoupling capacitors is problematic for CMP and lithography due to insufficient depth of focus (DOF). In this study, we first review and develop estimates for the decoupling capacitor and area fill insertions and propose an imitation dummy pattern comprising decoupling capacitors. We then perform an analysis to determine if there is an effective decrease in voltage drop without diminished yield. Finally, we evaluate the proposed techniques using layout test cases from industry.

LSI Logic's OPC package, Molotof, integrated into several RET flows has been successfully applied for strong phase shift mask simulation and optimization. Molotof simulator was used to predict sPSM imaging performance in response to statistical errors of alternating phase shift reticle manufacturing. Mask manufacturing errors were reproduced by generating a virtual gds mask with random values of sPSM control parameters such as phase depth, phase width and phase intensity. By measuring critical dimensions and image placement errors of a simulated aerial image for each random event, the image printability performance was calculated. The approach allows for quantitative evaluation and optimization of a strong PSM manufacturing specification by analyzing the distributions of critical dimensions and image placement errors. 2D-model, metrology and simulation flow for performing statistical analysis are discussed. Sensitivity to a single parameter variation and full statistical analysis of the 90nm poly line imaging performance affected by manufacturing errors is presented. The optimum range of phase depth, phase width and phase intensity, yielded 100% of critical dimensions and image placement errors, complying with 90nm technology design rules was found in simulation. Simulation results are confirmed by empirical data.

Dark field Alternating Aperture Phase Shift Mask (AAPSM) technology has developed into an enabling Resolution Enhancement Technology (RET) in the sub-100nm semiconductor device era. As phase shift masks are increasingly used to resolve features beyond just the most critical (for example transistor gates on the poly layer) the probability of phase conflicts (same phase across a feature) has increased tremendously. It has become imperative to introduce design practices that enable the semiconductor fabrication to take advantage of the improved performance that AAPSM delivers. In this paper we analyze the different causes for phase conflicts and the appropriate methods for detecting them, thus building the basis for the Hybrid AAPSM compliance flow. This approach leverages the strengths of existing DRC tools and the AAPSM conversion software. The approach is effective for minimizing the area penalty, thus very effective for density driven designs. By design, it is suited for custom or semi-custom layouts.