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3 May 2004 Combining OPC and design for printability into 65-nm logic designs
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The patterning of logic layouts for the 65nm and subsequent device generations will require the implementation of new capabilities in process control, optical proximity correction (OPC), resolution enhancement technique (RET) complexity, and lithography-design interactions. Many of the methods used to implement and verify these complex interactions can be described as design for manufacturability (DFM) techniques. In this paper we review a wide range of existing non-lithographic and lithographic DFM techniques in the semiconductor industry. We also analyze existing product designs for DFM technique implementation potential and propose new design methods for improving lithographic capability.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kevin D. Lucas, Chi-Min Yuan, Robert Boone, Kirk Strozewski, Jason Porter, Ruiqi Tian, Karl Wimmer, Jonathan Cobb, Bill Wilkinson, and Olivier Toublan "Combining OPC and design for printability into 65-nm logic designs", Proc. SPIE 5379, Design and Process Integration for Microelectronic Manufacturing II, (3 May 2004);

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