Layout engineering is the link in the design flow with the highest degree of freedom for manufacturability optimization.
Generating correct lithography-ready mask data as part of layout design would significantly shorten product’s time to
market. Until recently, however, a layout designer has no way of evaluating the manufacturability beyond design rules.
In this paper, we propose to integrate a comprehensive manufacturability preview capability into the layout design
environment. Based on the feedback from process simulation, a correct by construction approach for generating
manufacturing friendly layout is proposed. It consists of selective mask optimization and process weak spot detection.
We demonstrate the advantage of correct process construction using MOSIS standard cell library and discuss its future
Qi-De Qian, Qi-De Qian,
"DFM through correct process construction", Proc. SPIE 5379, Design and Process Integration for Microelectronic Manufacturing II, (3 May 2004); doi: 10.1117/12.535496; https://doi.org/10.1117/12.535496