3 May 2004 Extending aggressive low-k1 design rule requirements for 90-nm and 65-nm nodes via simultaneous optimization of NA, illumination, and OPC
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Proceedings Volume 5379, Design and Process Integration for Microelectronic Manufacturing II; (2004); doi: 10.1117/12.536982
Event: Microlithography 2004, 2004, Santa Clara, California, United States
Abstract
Under low-k1 patterning constraints, it has been a challenge for the lithography process to meet the aggressive IC design rule requirements for the 90nm and the upcoming 65nm nodes. From the imaging perspective, we see the geometric design rules are largely governed by numerical aperture (NA), illumination settings, and OPC for any resolution enhancement technique (RET) applied mask. We report a case study of exploring a set of process feasible design rule criteria based on a state-of-the-art μProcessor chip that contains three different styles of circuit design - standard library cell (SLC), random logic (RML), and SRAM. To keep the packing density higher for SRAM, the critical criteria for design rules involve achievable minimum pitch, sufficient area of contact-landing pad, minimum line end shortening (LES) to ensure poly endcap, and preferably to have optimum pitch for the placement of Scattering Bars (SB). For RML, the goal is to achieve the printing of ever smaller critical dimension (CD) with a greater CD uniformity control. The SLC should be designed to be comparable with both RML and SRAM devices. Hence, the design rule constraints for CD, space, line end, minimum pitch, and SB placement for SLC cell is critically confined. Unlike the traditional method of assuming a linear scaling for the design rule set, we explore achievable design rule criteria for very low k1 imaging by simultaneously optimizing NA, illumination settings, and OPC (for the optimum placement of SB) for a calibrated process. This is done by analyzing the CD control and the maximum overlapped process window for critical lines, spaces, line ends, and with the respective k1 factor for the three types of circuits. For 90nm node with k1 as low as 0.36, a feasible set of design rules for the μProcessor chip can be obtained using 6% attPSM with 6% exposure latitude at 400nm of overlapped depth of focus. Using the similar approach for the scaled down 65nm 6% attPSM, it resulted inadequate process latitude under a set of desired design rule constraints for critical pitch, CD, line end, minimum space, and SB placement. Hence for 65nm case, a CPL mask was used instead, as CPL (100% transmission) has the inherent capability of printing very thin line. The critical design rule criteria for SRAM, RML and SLC were revisited to ensure a large enough process margin.
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Sabita Roy, Douglas J. Van Den Broeke, J. Fung Chen, Armin Liebchen, Ting Chen, Stephen D. Hsu, Xuelong Shi, Robert John Socha, "Extending aggressive low-k1 design rule requirements for 90-nm and 65-nm nodes via simultaneous optimization of NA, illumination, and OPC", Proc. SPIE 5379, Design and Process Integration for Microelectronic Manufacturing II, (3 May 2004); doi: 10.1117/12.536982; http://dx.doi.org/10.1117/12.536982
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KEYWORDS
Diffractive optical elements

Optical proximity correction

Calibration

Critical dimension metrology

Stanford Linear Collider

Photomasks

Fiber optic illuminators

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