3 May 2004 Patterning sub-50-nm Fin-FET using KrF lithography tool
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A method to fabricate a very thin channel body Fin-FET and Tri-gate MOSFET is presented. 8% Attenuated Phase-shift mask (APSM) and single phase chrome-less mask (CLM) techniques are evaluated to pattern fins in sub-50 nm regime using KrF lithography scanner with a maximum numerical aperture of 0.68. Some of the issues of single phase CLM technique with respect to fin patterning are highlighted. Dual Exposure With Shift (DEWS)’ is introduced to pattern gate lines down to 80 nm using binary mask.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Navab Singh, Navab Singh, S. Jagar, S. Jagar, Sohan Singh Mehta, Sohan Singh Mehta, Moitreyee Mukherjee Roy, Moitreyee Mukherjee Roy, Rakesh Kumar, Rakesh Kumar, N. Balasubramanian, N. Balasubramanian, } "Patterning sub-50-nm Fin-FET using KrF lithography tool", Proc. SPIE 5379, Design and Process Integration for Microelectronic Manufacturing II, (3 May 2004); doi: 10.1117/12.536040; https://doi.org/10.1117/12.536040


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