23 July 1985 Lithography Limited Yield Analysis
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A computer program has been developed for calculating statistical layout design rules for integrated circuits. The program also calculates the sampling plan required to verify the confidence levels of alignment and circuit element dimensions at develop inspection. The inherent speed and computational accuracy of the computer offers the user a choice of confidence levels depending upon circuit configuration and critical alignments in the process. Finally, the program calculates overall circuit yields as a function of lithography limited margin violations.
© (1985) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Clark Beck, Clark Beck, } "Lithography Limited Yield Analysis", Proc. SPIE 0538, Optical Microlithography IV, (23 July 1985); doi: 10.1117/12.947759; https://doi.org/10.1117/12.947759

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