29 July 2004 0.8V ultralow-power CMOS analog multiplexer for remote biological and chemical signal processing
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Abstract
A CMOS analog multiplexer circuit has been designed for operation at 0.8 V. The circuit consists of transmission gates as switches and an inverter. MOSFETs in the design of multiplexer use the dynamic body bias method. The forward body bias is limited to no more than 0.4 V to avoid CMOS latch-up. The reverse body bias is limited to 0.4 V and allows the MOSFET to turn-off fully and suppresses the sub-threshold leakage. The improved dynamic threshold MOSFET (DTMOS) inverter is engaged to achieve low voltage operation. The CMOS multiplexer chip was designed in standard 1.5 μm n-well CMOS technology and simulated using SPICE. Excellent agreement was obtained between the simulated output waveform and corresponding experimentally measured behavior. The power dissipation is close to 70 nW and signal-to-leakage ratio is 120 dB. The proposed low voltage, ultra-low power analog multiplexer would find application for on-chip neural microprobes and other applications.
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Chuang Zhang, Chuang Zhang, Ashok Srivastava, Ashok Srivastava, Pratul K. Ajmera, Pratul K. Ajmera, } "0.8V ultralow-power CMOS analog multiplexer for remote biological and chemical signal processing", Proc. SPIE 5389, Smart Structures and Materials 2004: Smart Electronics, MEMS, BioMEMS, and Nanotechnology, (29 July 2004); doi: 10.1117/12.539066; https://doi.org/10.1117/12.539066
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