Computer Aided Design (CAD) is an essential tool in circuits and systems design and modeling. With the current advances in computer technology, it is becoming more feasible to obtain good and accurate models in a reasonable time. For transistors, it is important to have accurate small- and large-signal models to achieve good predictions of system behavior. Automating the model selection process helps to speed the design cycle. In this paper, we describe the process of generating optimal large-signal model for MESFETs based on an optimal small-signal topology and using I-V and transconductance measurement data. This is achieved by, first, generating an optimal small-signal model and topology for a MESFET based on a given S-parameter experimental data, and using TopFinder, a CAD tool we developed. The methodology is demonstrated on a GaAs power FET based on Curtice, Materka, or Statz DC models. The optimal large-signal model is decided upon by using a least-square optimality metric that combines both the fitting of the I-V curves as well as their derivatives. The metric showed that the Materka model based on an optimal small-signal topology was roughly 50% better than the Curtice model.