20 August 2004 EUVL mask challenges and how International SEMATECH is addressing them
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Proceedings Volume 5446, Photomask and Next-Generation Lithography Mask Technology XI; (2004) https://doi.org/10.1117/12.557813
Event: Photomask and Next Generation Lithography Mask Technology XI, 2004, Yokohama, Japan
Many technological challenges exist for the timely introduction of successive generations of integrated circuits with decreasing feature size. Lithography at dimensions commensurate with those described in the International Roadmap for Semiconductors at technology nodes with half pitch ≤45nm will require complex masks for 193nm immersion or EUV masks. ISMT has a five-year alliance with the State University of New York at Albany to develop EUV mask blanks and EUV resist. A process line to develop low defect extreme ultraviolet (EUV) mask blank multilayers is operational. ISMT is also working with commercial suppliers, who are fabricating EUV mask substrates and multilayer-coated mask blanks. Tools and processes for fabricating, inspecting, reviewing defects and repairing defects for EUV mask blanks are being developed as well. In addition, standards for EUV mask blank requirements and strategies for maintaining defect free EUV masks are being investigated.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Scott Daniel Hector, Scott Daniel Hector, Kevin Kemp, Kevin Kemp, } "EUVL mask challenges and how International SEMATECH is addressing them", Proc. SPIE 5446, Photomask and Next-Generation Lithography Mask Technology XI, (20 August 2004); doi: 10.1117/12.557813; https://doi.org/10.1117/12.557813


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