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20 August 2004 Full-chip manufacturing reliability check implementation for 90-nm and 65-nm nodes using CPL and DDL
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Proceedings Volume 5446, Photomask and Next-Generation Lithography Mask Technology XI; (2004)
Event: Photomask and Next Generation Lithography Mask Technology XI, 2004, Yokohama, Japan
Advanced masks such as CPL and DDL are the two leading low k1 lithography enablers for the upcoming 90nm and 65nm nodes. The mask generation methodologies for both have been clearly defined with convincing wafer printing results. We found that full-chip optical proximity correction (OPC) is by all means one of most critical components for CPL and DDL. The OPC process ensures the correct 2D pattern shapes and to achieve the desired CD to be printed on wafer with sufficient process margin. However, in addition to the already complex mask data generation, the OPC process further increases mask data complexity and more prone to data handling errors. It is therefore highly desirable to perform full-chip Manufacturing Reliability Check (MRC) prior to mask making. From our viewpoints, MRC needs to cover two goals: first is to single out the “weak printing spots” or to map out the treated CPL/DDL features with unacceptable DOF and exposure latitude so that the corrective actions can be taken, and second is to ensure printing of the entire chip to meet the process requirement. The success of MRC process depends on a well-trained modeling algorithm, which should be well capable of predicting the optical and resist behavior correctly across the entire chip. To perform a production worthy MRC for CPL (with two mask writing steps) and DDL (with two exposure masks), one must have a full knowledge of the mask generation principles for both. In this paper, we demonstrate a working scheme that has been designed to capture a variety of geometric variations on the treated mask layout that could lead to unacceptable printing performance. In this scheme, the MRC for CPL and DDL are handled in two separate modules and the final MRC data is characterized and classified into specified category. The predicted error points were reported and displayed through statistical analysis. Process tolerance during mask making was also taking into consideration. For the optimum MRC performance, we try to balance the wafer pattern fidelity, data complexity, and the mask cost. The fix suggestions for the failure discovered can be automatically proposed for some of specified layouts. This MRC method could also be applied to all types of PSM or multi-exposure mask.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Michael Hsu, Thomas L. Laidig, Kurt E. Wampler, Stephen D. Hsu, Xuelong Shi, J. Fung Chen, Douglas J. Van Den Broeke, and Frank Hsieh "Full-chip manufacturing reliability check implementation for 90-nm and 65-nm nodes using CPL and DDL", Proc. SPIE 5446, Photomask and Next-Generation Lithography Mask Technology XI, (20 August 2004); doi: 10.1117/12.557792;

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