Structure and data processing for PEL mask compatible with image placement accuracy in the 65-nm node and beyond

Kohichi Nakayama; Kensuke Tsuchiya; Shinji Omori; Hidetoshi Ohnuma

doi:10.1117/12.557776

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20 August 2004 Structure and data processing for PEL mask compatible with image placement accuracy in the 65-nm node and beyond

Kohichi Nakayama, Kensuke Tsuchiya, Shinji Omori, Hidetoshi Ohnuma

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Proceedings Volume 5446, Photomask and Next-Generation Lithography Mask Technology XI; (2004) https://doi.org/10.1117/12.557776
Event: Photomask and Next Generation Lithography Mask Technology XI, 2004, Yokohama, Japan

Abstract

Image placement (IP) error of a 1x stencil mask is a concern for proximity electron beam lithography (PEL) when considering its application in the 65 and 45-nm nodes. According to our preliminary overlay budget for the 65-nm node, the global IP over the mask and the local IP within each membrane should be kept less than 10 and 7 nm, respectively to fulfill the total overlay accuracy of 23 nm. In this paper, we demonstrate the mask structure and the data processing method that enables the mask to be fully compatible with the local IP requirement in those technology nodes.

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Kohichi Nakayama, Kensuke Tsuchiya, Shinji Omori, and Hidetoshi Ohnuma "Structure and data processing for PEL mask compatible with image placement accuracy in the 65-nm node and beyond", Proc. SPIE 5446, Photomask and Next-Generation Lithography Mask Technology XI, (20 August 2004); https://doi.org/10.1117/12.557776

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