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8 September 2004 Comparison between electrical and optical clock distribution for CMOS integrated circuits
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Downscaling the CMOS technology is expected to encounter a metallic interconnect bottleneck in the near future due to the increasing delays of global on-chip interconnects, problems of signal integrity and timing uncertainty (skew and jitter) as well as power consumption. The possible silicon-compatible monolithic integration of optical on-chip interconnects is described as an alternative solution. It is shown that integrated optics using SOI single-mode waveguides, Si-based modulators, and Ge photodetectors offers a feasible way to distribute global signals such as the global clock across a chip. Taking into account the photodetectors followed by a CMOS-inverter-based transimpedance front-end amplifier with additional gain stages to ensure sufficient voltage swing, optical interconnects characteristics are compared with the performances of future metallic global interconnects recently published in the literature. The main advantages brought by optics include signal propagation with negligible distortion over cm-long distances, reduction of total chip power consumption, reduced delay, skew and jitter if compared with electrical repeated lines, and a lower sensitivity to temperature variations.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Eric Cassan, Delphine Marris, Mathieu Rouviere, Suzanne Laval, Laurent Vivien, and Alain Koster "Comparison between electrical and optical clock distribution for CMOS integrated circuits", Proc. SPIE 5453, Micro-Optics, VCSELs, and Photonic Interconnects, (8 September 2004);

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