16 August 2004 Characterization of waferstepper and process-related front- to backwafer overlay errors in bulk micromachining using electrical overlay test structures
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Abstract
To validate the Front- To Backwafer Alignment (FTBA) calibration and to investigate process related overlay errors, electrical overlay test structures are used that requires FTBA [1]. Anisotropic KOH etch through the wafer is applied to transfer the backwafer pattern to the frontwafer. Consequently, the crystal orientation introduces an overlay shift. A double exposure method is presented to separate the process-induced shift from the FTBA shift. The process induced overlay shift can run up to 3 μm, large compared to the expected FTBA error (around 0.1 μm). The measured overlay distribution is 0.45 μm (3σ), this includes both waferstepper and process related overlay errors. The overlay distribution, corrected for waferstepper related overlay errors, like lens distortion, resembles the overlay distribution of the bulk micromachining (BMM) process; 0.26 μm (3σ). The procedures described in this work provide a quantitative method of describing the waferstepper and process related front to backwafer overlay errors.
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Henk W. van Zeijl, Frans G. C. Bijnen, John Slabbekoorn, "Characterization of waferstepper and process-related front- to backwafer overlay errors in bulk micromachining using electrical overlay test structures", Proc. SPIE 5455, MEMS, MOEMS, and Micromachining, (16 August 2004); doi: 10.1117/12.545900; https://doi.org/10.1117/12.545900
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