Electrical low frequency excess noise or 1/f noise measurements provide strong means to diagnose the quality and reliability of the devices in semiconductor devices. However the exact nature of the noise sources are not clearly understood yet. In this report, existing models for low frequency excess electrical noise in poly-Si thin-film transistors is scrutinized and a new model is proposed, in particular, for large grain poly-crystalline thin-film transistors. Major noise sources are supposed to be located in the grain boundary region and the grain boundary is modeled as two independent Schottky diode connected face-to-face. As the gate bias increases the grain boundary barrier height decreases and the conduction and therefore the noise generation in the grain bulk region becomes important. Therefore, at low gate bias, grain boundary plays important role in conduction and noise generation, and at high bias, the number fluctuation involving the oxide traps leading to flat band fluctuation (unified model for crystalline-Si MOSFET's) will dominate the noise generation. We calculated the critical gate bias (or barrier height) that severs these two different noise generation regimes. Recently reported experimental results are explained with this model.
Jung Il Lee, Jung Il Lee,
"Barrier height dependence of low-frequency noise in poly-Si thin film transistors", Proc. SPIE 5470, Noise in Devices and Circuits II, (25 May 2004); doi: 10.1117/12.547191; https://doi.org/10.1117/12.547191