25 May 2004 Noise modeling and performance in 0.15-μm fully depleted SOI MOSFET
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Proceedings Volume 5470, Noise in Devices and Circuits II; (2004) https://doi.org/10.1117/12.546669
Event: Second International Symposium on Fluctuations and Noise, 2004, Maspalomas, Gran Canaria Island, Spain
Abstract
This paper is intended to describe on one part theoretical results issued from a physical noise modeling and on the other part the noise performance of Fully Depleted (FD) SOI MOSFET of 0.15 μm gate length. In the theoretical part, the physical noise model is applied to two distinct applications; first to study the influence of the microscopic diffusion noise sources definition (located in the channel device) on the noise performance, second to check the concept of un-correlated noise sources, if one uses an input noise voltage and output drain noise current representation. In the experimental part, both bias and frequency dependences of the measured noise performances of the 0.15 μm gate length fully depleted (FD) SOI MOSFET (OKI technology) are presented, and a comparison with the results issued from the physical noise model is proposed.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Guillaume Pailloncy, Guillaume Pailloncy, Benjamin Iniguez, Benjamin Iniguez, Gilles Dambrine, Gilles Dambrine, Morin Dehan, Morin Dehan, Jean-Pierre Raskin, Jean-Pierre Raskin, Hideaki Matsuhashi, Hideaki Matsuhashi, Pierre Delatte, Pierre Delatte, Francois Danneville, Francois Danneville, } "Noise modeling and performance in 0.15-μm fully depleted SOI MOSFET", Proc. SPIE 5470, Noise in Devices and Circuits II, (25 May 2004); doi: 10.1117/12.546669; https://doi.org/10.1117/12.546669
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