25 May 2004 Noise of analog SOI CMOS integrated circuits at millimeter wave frequencies
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Proceedings Volume 5470, Noise in Devices and Circuits II; (2004) https://doi.org/10.1117/12.546373
Event: Second International Symposium on Fluctuations and Noise, 2004, Maspalomas, Gran Canaria Island, Spain
In this paper, the noise properties of transistors on 90 nm silicon on insulator (SOI) and bulk CMOS technologies are investigated. At 20 GHz, the SOI and bulk devices have minimum noise figures of 1 dB and 2.3 dB, respectively, demonstrating the superior performance of the SOI technology. The corresponding maximum available gain is 13 dB and 12 dB, respectively. For the first time, the drain and gate noise coefficients of shortchannel SOI devices are extracted yielding values of 2.15 and 1.7, respectively. Theoretical aspects are discussed to identify the main noise sources and to gain insights for optimizations. Furthermore, examples of analog monolithic integrated circuits fabricated on SOI technology are presented. Measured results are a noise figure of 4 dB for a low noise amplifier (LNA) at 40 GHz, a single side band noise figure of 9 dB for a passive mixer at 40 GHz and a phase noise of -90 dBc at 1 MHz offset for an voltage controlled oscillator (VCO) at 60 GHz. To the knowledge of the authors, these are the best noise performances achieved to date for CMOS based transistors and circuits at millimeter wave frequencies.
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Frank Ellinger, Frank Ellinger, } "Noise of analog SOI CMOS integrated circuits at millimeter wave frequencies", Proc. SPIE 5470, Noise in Devices and Circuits II, (25 May 2004); doi: 10.1117/12.546373; https://doi.org/10.1117/12.546373

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