26 October 2004 Automated synthesis of Dadda multipliers
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Abstract
Although Dadda multipliers offer the greatest speed potential with a delay proportional to log(n), they are not often used in everyday designs because of their irregular structure and the ensuing difficulty this entails in their implementation. This paper presents a program which automatically generates HDL code describing a Dadda multiplier of specified size. The resulting HDL code is then synthesized to a generic library in the TSMC13G process (0.13um). It is observed that delay increases only marginally when increasing the multiplier size from 16 to 64 bits, while total area increases drastically.
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Travis Lanier, Travis Lanier, Jacob Wilcox, Jacob Wilcox, Earl E. Swartzlander, Earl E. Swartzlander, } "Automated synthesis of Dadda multipliers", Proc. SPIE 5559, Advanced Signal Processing Algorithms, Architectures, and Implementations XIV, (26 October 2004); doi: 10.1117/12.559866; https://doi.org/10.1117/12.559866
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