Complementary Phase Shift Mask (c:PSM) has been a key photolithographic technique employed by chip makers, including Motorola, to fabricate 130nm-node devices. Advancing from the 130nm to 90nm technology generation, the c:PSM process needs fundamental improvements in order to meet new challenges such as tighter CD tolerance, smaller pitches, etc. In this paper we describe the challenges and our efforts to develop a c:PSM process for the 90nm technology, with a particular emphasis on the gate layer patterning. The significantly increased pattern density led to our strategy to phase shift not only gates but also some routing lines. As a result, more features are prone to phase conflicts. These phase conflicts have been avoided by enforcing more constrains on design rules, optimizing shifter/trim parameters, improving the coloring methods in the software, and even manually handling special cases. Model-based OPC has been applied to both masks with models rigorously calibrated to resist data. Small budget for CD variation imposes stringent requirements on both model accuracy and algorithm robustness. The double exposure process required by the c:PSM process aggravates the difficulties, by introducing issues such as different process conditions in the two exposures, intensity imbalance, connection between segment movements in the two masks, etc. The models and correction algorithm have been tuned to accommodate these issues. Both rule-based and simulation-based verification have been utilized to check mask manufacturability, susceptibility to defects, and pattern fidelity. In particular, a structural checking mechanism has been built for complexities created by the double exposure process. Significant effects from intensity imbalance have been observed on wafer at small pitches. Work is under way to alleviate the intensity imbalance by using different mask making techniques.