Double Dipole Lithography (DDLä) has been demonstrated to be capable of patterning complex 2D devices patterns. [1,2,3] Due to inherently high aerial image contrast from dipole illumination, we have found that it can meet lithography manufacturing requirements, such as line edge roughness (LER), and critical dimension uniformity (CDU), for the upcoming 65nm node using ArF binary chrome masks. For patterning at k1 below 0.35, DDL is one of the promising resolution enhancement techniques (RET), which can offer process latitudes that are comparable to more costly alternatives such as two-exposure alternating PSM. To use DDL for printing actual IC devices, the original design data must be converted into a "vertical (V)" mask and a "horizontal (H)" mask for the respective X-dipole and Y-dipole exposures. We demonstrated that our model-based DDL mask data processing methodology is capable of converting complex 2D logic and memory designs into dipole-compatible mask layouts. [2,3] Due to the double exposure, stray light must be well controlled to ensure uniform printing across the entire chip. One intuitive solution to minimize stray light is to apply large patches of chrome in the open field areas in order to reduce the background (non-pattern area) exposure level. Unfortunately, this is not viable for a clear-field poly gate mask as it incorporates a positive photoresist process. We developed an innovative and practical background-shielding scheme called sub-resolution grating block (SGB), which is part of the DDL layout conversion method for full-chip application. This technique can effectively minimize the impact of long-range stray light on critical features during the two exposures. Reticles inspection is another important issue for the implementation of DDL technology. In this work, we reported a methodology on how to characterize defects and optimize inspection sensitivity for DDL RET reticles.