LER characterization and impact on 0.13-µm lithography for OPC modeling

Peter Nikolsky; Rama Tweg; Enna Altshuler; Eitan N. Shauly

doi:10.1117/12.568999

6 December 2004 LER characterization and impact on 0.13-μm lithography for OPC modeling

Peter Nikolsky, Rama Tweg, Enna Altshuler, Eitan N. Shauly

Proceedings Volume 5567, 24th Annual BACUS Symposium on Photomask Technology; (2004) https://doi.org/10.1117/12.568999
Event: Photomask Technology, 2004, Monterey, California, United States

Abstract

This paper presents Line Edge Roughness (LER) characterization for Tower Semiconductor 0.13um Standard Logic technology with advanced OPC modeling. First the applicability of top-view CD-SEM and AFM for LER measurement of poly-Si transistor gate characterization is studied. Then the influence of aerial image contrast and the gradient of the photoactive component on LER is reviewed and the possibility of minimizing LER by optimizing process conditions is considered. Finally the impact of LER on OPC model accuracy is reviewed. Model predictability with and without LER taken into account is compared.

Citation Download Citation

Peter Nikolsky, Rama Tweg, Enna Altshuler, and Eitan N. Shauly "LER characterization and impact on 0.13-μm lithography for OPC modeling", Proc. SPIE 5567, 24th Annual BACUS Symposium on Photomask Technology, (6 December 2004); https://doi.org/10.1117/12.568999

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