6 December 2004 Maintaining lithographic quality during OPC for low k1 and MEEF processes constrained by mask dimensional rules
Author Affiliations +
Abstract
Mask fabrication rules can interfere with the ability of OPC and RET shape generation to achieve the best lithographic quality on silicon. With low k1 lithography, ideal correction shapes dictated by lithography-based simulation frequently violate mask geometry constraints. Because the scaled spatial bandwidth of the wafer lithography process is lower than that of the mask process there are some degrees of freedom in OPC shape generation to optimize for lithographic accuracy and mask compliance together. In this paper we discuss strategies to embed mask rule compliance in correct-by-construction model-based OPC.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Christopher M. Cork, Christopher M. Cork, Lawrence S. Melvin, Lawrence S. Melvin, Michael Miller, Michael Miller, Robert M. Lugg, Robert M. Lugg, Michael L. Rieger, Michael L. Rieger, } "Maintaining lithographic quality during OPC for low k1 and MEEF processes constrained by mask dimensional rules", Proc. SPIE 5567, 24th Annual BACUS Symposium on Photomask Technology, (6 December 2004); doi: 10.1117/12.568550; https://doi.org/10.1117/12.568550
PROCEEDINGS
7 PAGES


SHARE
RELATED CONTENT

Finding the needle in the haystack using full chip...
Proceedings of SPIE (October 20 2006)
Enriching design intent for optimal OPC and RET
Proceedings of SPIE (August 01 2002)
Programmable RET mask layout verification
Proceedings of SPIE (December 27 2002)
The rising cost and complexity of RETs
Proceedings of SPIE (May 03 2004)

Back to Top